library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use work.FAW_TYPES.all;

entity RSP_ShiftRegister is
        Port ( 
                          clk_rspsr : in  STD_LOGIC;
           data_in_rspsr : in  STD_LOGIC_VECTOR (7 downto 0);
                          we_rspsr : in STD_LOGIC;
           oe_rspsr : in  STD_LOGIC_VECTOR (N_SP_IN_ROW-1 downto 0);
                          oe_rspsr_row : in STD_LOGIC;
           sclear_rspsr : in  STD_LOGIC;
                          data_out_rspsr : out  RSPSR_SR_DATA_BUS
                          );
end RSP_ShiftRegister;

architecture Behavioral of RSP_ShiftRegister is


component SR_CELL is
                port(
                        d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                        clk : IN STD_LOGIC;
                        sclr : IN STD_LOGIC;
                        q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
                );
        end component;

        SIGNAL INTERNAL_BUS : RSPSR_SR_DATA_BUS;
        signal internal_clock : std_logic;

begin

        ShiftRegisterFirstCell : SR_CELL
                port map(
                        clk=>internal_clock,
                        d=>data_in_rspsr,
                        q=>INTERNAL_BUS(0),
                        sclr=>sclear_rspsr
                );
        
        ShiftRegisterInternal : for i in 1 to N_SP_IN_ROW-1 generate
                comp: SR_CELL
                port map(
                        clk=>internal_clock,
                        d=>INTERNAL_BUS(i-1),
                        q=>INTERNAL_BUS(i),
                        sclr=>sclear_rspsr
                );
        end generate ShiftRegisterInternal;

        processo:process(clk_rspsr)
                
        variable DATA_OUT: RSPSR_SR_DATA_BUS;
                begin
                        if (clk_rspsr'event and clk_rspsr='1') then
                                if(we_rspsr='1')then
                                        internal_clock<=clk_rspsr;
                                else
                                        internal_clock<='0';
                                end if;
                                
                                for i in 0 to N_SP_IN_ROW-1 loop
                                        if(oe_rspsr_row='1' and oe_rspsr(i)='1')then
                                                DATA_OUT(i):=INTERNAL_BUS(i);
                                        else
                                                DATA_OUT(i):= (others=>'Z');
                                        end if;
                                end loop;       
                                data_out_rspsr<=DATA_OUT;
                        end if;
                        
--                        if (clk_rspsr_false'event and clk_rspsr_false='1') then
--                                        internal_clock<='0';
--                        end if;
                end process;

end Behavioral;